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4)D/A輸出單元
D/A輸出單元負責將已累加/減數據轉換為模擬信號輸出。D/A輸出單元時序同步于控制脈沖。如果掃描控制器硬件資源不多,可以給每一個控制量單獨配置一個D/A轉換器;否則,可以將這些控制量先緩存起來再通過一個D/A轉換器輸出以減少硬件成本。
5)觸發(fā)單元
觸發(fā)單元接收到掃描使能控制字后控制步進脈沖發(fā)生單元使能端有效,步進脈沖發(fā)生單元開始工作,進而使得整個掃描控制器運轉起來。當觸發(fā)單元內計數器的計數值與接收到的用于計算掃描時間的計數量相同時表明掃描過程已經完成,這時觸發(fā)單元控制步進脈沖發(fā)生單元使能端失效,步進脈沖發(fā)生單元停止工作,掃描過程結束。另外,在掃描開始前觸發(fā)單元接收控制字產生全局中斷信號,通過中斷處理單元通知運算單元調用各硬件控制量的初始DAC值。
6)中斷處理單元
中斷處理單元根據預先設定的中斷優(yōu)先級別決定控制運算單元內各模塊的先后順序。中斷處理單元由中斷寄存器、中斷識別模塊、復位處理模塊三部分組成。組成框圖見圖2所示。
中斷處理過程如下:首先,四種中斷分別緩存入四個中斷寄存器。中斷寄存器使用FIFO存儲單元可以儲存多個中斷,利用FIFO存儲單元內部自身的標志位作為邏輯判斷依據可以簡化我們的設計。其次,中斷識別模塊檢測各FIFO存儲單元的空標志位。如果有任意一個FIFO存儲單元的空標志位為O,則說明有中斷產生,那么中斷識別模塊將按中斷優(yōu)先級別排序,并產生一個脈沖通知與zui高中斷級別相對應的運算單元內的數據調用模塊從RAM中讀取下一段控制量的初始值。再次,數據調用模塊完成讀取任務后返回給復位處理模塊一個處理程序完成標志。復位處理模塊在收到處理程序完成標志后根據輸出中斷類別產生讀脈沖至空標志位為O且中斷優(yōu)先級別zui高的中斷寄存器中。此時,中斷寄存器的空標志位有可能發(fā)生變化。zui后,中斷識別模塊再次檢測所有的空標志是否都為1,如果不是,中斷處理單元繼續(xù)上述過程直到所有的空標志都為1。中斷處理過程結束。
7)步進脈沖發(fā)生單元
步進脈沖發(fā)生單元內包含多個計數器,計數使能由觸發(fā)單元控制,計數器的模從地址譯碼/數據緩存單元讀取。每隔一定時間,步進脈沖發(fā)生單元產生計數脈沖作為累加/減器的時鐘并由運算單元內計數器計數。
4 設計實例
以某型號微波毫米波接收機為例。在此接收機中,系統(tǒng)總線設計為串行總線,需要控制的變量有YIG振蕩器頻率、YIG濾波器中心頻率、平坦度補償數據和預選器帶寬控制電壓。選用Altera公司的EplkSOQC208—3芯片作為數字掃描控制器芯片,IDT71V016SA20Y作為RAM存儲芯片,AD7538KR、DAC8412作為DAC轉換芯片。
經測量,YIG振蕩器頻率開環(huán)控制精度達到5MHz(接收機鎖相環(huán)的鎖頻范圍可達80MHz),YIG濾波器中心頻率控制精度達到3MHz(YIG濾波器3dB帶寬zui小處40MHz),平坦度補償值誤差小于O.2dB,預選器帶寬誤差小于帶寬2%。數字掃描控制器選用60MHz時鐘作為外部時鐘,在zui忙碌情況下(四種中斷同時到來),完成四種中斷處理總時間小于5μs。
通過仿真和測試數字掃描控制器僅使用了FPGA內約70%的資源,可以為今后的模塊擴展留有余地。
5 結束語
對于掃描控制器自身硬件來說,我們可以通過將控制量曲線劃分更多段、更加逼近真實曲線,達到提高控制精度的目的;通過選用高檔的FPGA芯片并提高系統(tǒng)工作時鐘,達到提高控制速度的目的。但在實際使用過程中,我們還必須綜合考慮硬件自身的性能(如YIG器件磁滯效應、機械開關切換時間、中頻濾波器響應時間等)、軟件設計復雜度、要求的性能指標等多組因素對掃描控制精度、速度的影響,合理選擇劃分段數及工作時鐘,zui大限度挖掘出接收機潛能。
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