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 4)D／A輸出單元
D／A輸出單元負(fù)責(zé)將已累加／減數(shù)據(jù)轉(zhuǎn)換為模擬信號(hào)輸出。D／A輸出單元時(shí)序同步于控制脈沖。如果掃描控制器硬件資源不多，可以給每一個(gè)控制量單獨(dú)配置一個(gè)D／A轉(zhuǎn)換器；否則，可以將這些控制量先緩存起來再通過一個(gè)D／A轉(zhuǎn)換器輸出以減少硬件成本。
5)觸發(fā)單元
觸發(fā)單元接收到掃描使能控制字后控制步進(jìn)脈沖發(fā)生單元使能端有效，步進(jìn)脈沖發(fā)生單元開始工作，進(jìn)而使得整個(gè)掃描控制器運(yùn)轉(zhuǎn)起來。當(dāng)觸發(fā)單元內(nèi)計(jì)數(shù)器的計(jì)數(shù)值與接收到的用于計(jì)算掃描時(shí)間的計(jì)數(shù)量相同時(shí)表明掃描過程已經(jīng)完成，這時(shí)觸發(fā)單元控制步進(jìn)脈沖發(fā)生單元使能端失效，步進(jìn)脈沖發(fā)生單元停止工作，掃描過程結(jié)束。另外，在掃描開始前觸發(fā)單元接收控制字產(chǎn)生全局中斷信號(hào)，通過中斷處理單元通知運(yùn)算單元調(diào)用各硬件控制量的初始DAC值。
6)中斷處理單元
中斷處理單元根據(jù)預(yù)先設(shè)定的中斷優(yōu)先級(jí)別決定控制運(yùn)算單元內(nèi)各模塊的先后順序。中斷處理單元由中斷寄存器、中斷識(shí)別模塊、復(fù)位處理模塊三部分組成。組成框圖見圖2所示。

中斷處理過程如下：首先，四種中斷分別緩存入四個(gè)中斷寄存器。中斷寄存器使用FIFO存儲(chǔ)單元可以儲(chǔ)存多個(gè)中斷，利用FIFO存儲(chǔ)單元內(nèi)部自身的標(biāo)志位作為邏輯判斷依據(jù)可以簡(jiǎn)化我們的設(shè)計(jì)。其次，中斷識(shí)別模塊檢測(cè)各FIFO存儲(chǔ)單元的空標(biāo)志位。如果有任意一個(gè)FIFO存儲(chǔ)單元的空標(biāo)志位為O，則說明有中斷產(chǎn)生，那么中斷識(shí)別模塊將按中斷優(yōu)先級(jí)別排序，并產(chǎn)生一個(gè)脈沖通知與zui高中斷級(jí)別相對(duì)應(yīng)的運(yùn)算單元內(nèi)的數(shù)據(jù)調(diào)用模塊從RAM中讀取下一段控制量的初始值。再次，數(shù)據(jù)調(diào)用模塊完成讀取任務(wù)后返回給復(fù)位處理模塊一個(gè)處理程序完成標(biāo)志。復(fù)位處理模塊在收到處理程序完成標(biāo)志后根據(jù)輸出中斷類別產(chǎn)生讀脈沖至空標(biāo)志位為O且中斷優(yōu)先級(jí)別zui高的中斷寄存器中。此時(shí)，中斷寄存器的空標(biāo)志位有可能發(fā)生變化。zui后，中斷識(shí)別模塊再次檢測(cè)所有的空標(biāo)志是否都為1，如果不是，中斷處理單元繼續(xù)上述過程直到所有的空標(biāo)志都為1。中斷處理過程結(jié)束。
7)步進(jìn)脈沖發(fā)生單元
步進(jìn)脈沖發(fā)生單元內(nèi)包含多個(gè)計(jì)數(shù)器，計(jì)數(shù)使能由觸發(fā)單元控制，計(jì)數(shù)器的模從地址譯碼／數(shù)據(jù)緩存單元讀取。每隔一定時(shí)間，步進(jìn)脈沖發(fā)生單元產(chǎn)生計(jì)數(shù)脈沖作為累加／減器的時(shí)鐘并由運(yùn)算單元內(nèi)計(jì)數(shù)器計(jì)數(shù)。

4 設(shè)計(jì)實(shí)例
以某型號(hào)微波毫米波接收機(jī)為例。在此接收機(jī)中，系統(tǒng)總線設(shè)計(jì)為串行總線，需要控制的變量有YIG振蕩器頻率、YIG濾波器中心頻率、平坦度補(bǔ)償數(shù)據(jù)和預(yù)選器帶寬控制電壓。選用Altera公司的EplkSOQC208—3芯片作為數(shù)字掃描控制器芯片，IDT71V016SA20Y作為RAM存儲(chǔ)芯片，AD7538KR、DAC8412作為DAC轉(zhuǎn)換芯片。
經(jīng)測(cè)量，YIG振蕩器頻率開環(huán)控制精度達(dá)到5MHz(接收機(jī)鎖相環(huán)的鎖頻范圍可達(dá)80MHz)，YIG濾波器中心頻率控制精度達(dá)到3MHz(YIG濾波器3dB帶寬zui小處40MHz)，平坦度補(bǔ)償值誤差小于O．2dB，預(yù)選器帶寬誤差小于帶寬2％。數(shù)字掃描控制器選用60MHz時(shí)鐘作為外部時(shí)鐘，在zui忙碌情況下(四種中斷同時(shí)到來)，完成四種中斷處理總時(shí)間小于5μs。
通過仿真和測(cè)試數(shù)字掃描控制器僅使用了FPGA內(nèi)約70％的資源，可以為今后的模塊擴(kuò)展留有余地。

5 結(jié)束語(yǔ)
對(duì)于掃描控制器自身硬件來說，我們可以通過將控制量曲線劃分更多段、更加逼近真實(shí)曲線，達(dá)到提高控制精度的目的；通過選用高檔的FPGA芯片并提高系統(tǒng)工作時(shí)鐘，達(dá)到提高控制速度的目的。但在實(shí)際使用過程中，我們還必須綜合考慮硬件自身的性能(如YIG器件磁滯效應(yīng)、機(jī)械開關(guān)切換時(shí)間、中頻濾波器響應(yīng)時(shí)間等)、軟件設(shè)計(jì)復(fù)雜度、要求的性能指標(biāo)等多組因素對(duì)掃描控制精度、速度的影響，合理選擇劃分段數(shù)及工作時(shí)鐘，zui大限度挖掘出接收機(jī)潛能。

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